A universal optoelectronic imaging platform with wafer-scale
A universal optoelectronic imaging platform with wafer-scale integration of two-dimensional semiconductors Xinyu Wang 1 †, Die Wang 1 †, Yuchen Tian 1 †, Jing Guo 1, Jinshui
Optoelectronic-integrated 3D Chip
Home / Optoelectronic-integrated 3D Chip
Recently, an engineer team from Columbia University, Cornell University, and other institutions has successfully developed a novel three-dimensional (3D) optoelectronic chip by deeply integrating photonic technology with advanced complementary metal-oxide-semiconductor. Abstract—We demonstrate a dense, highly parallel, and scal-able multi-channel transceiver array for photonic chip-to-chip links. Advanced packaging technologies, such as 3D chiplets hetero-integration and co-packaged optics (CPO), have become crucial for further improving system performance. Currently, most solutions rely on silicon-based technologies, which alleviate some challenges but still face issues such as warpage. Here, we present a robust, chiplet-level heterogeneous integration of polymer-based circuits (CHIP), where several post-fabricated, ultrathin, polymer electronic, and optoelectronic chiplets are vertically bonded into one single chip at room temperature and then shaped into application-specific.
